Pg 75, figure of 64-bit word near bottom of page: bits 32, 33, and 35 should all be 0.

Pg 194, Figure 3.4, Diamond box at bottom should say "64th repetition?" inside box.

Pg 207: Double precision figure, the boundary between the exponent and the fraction should be between bits 51 and 52.

Pg 217: Step 2: the numbers are misaligned (9990 should be shifted one place to the left) and the sum should be 10212000.

Pg 242 Fallacy: The authors claim that shift right is not a division by a power of 2.  The question with integer division is what to do with the fractional part of the result.  The authors want to round towards 0, but don't state that in their fallacy.  What shift right of two's complement numbers does is divide by a power of 2 and truncate towards -infinity.  So shift right is a form of division by a power of 2 (where's my cigar?).

Pg 249: Questions 3.7 and 3.8 talk about 185 in 8-bit signed magnitude format; 185.  185 can't be represented in 8-bit signed magnitude format (185 has an 8-bit binary representation).  3.9 and 3.10 are also a bit suspect, too.

Pg 250 3.21: Question asks about MIPS instruction; should be updated to an ARM instruction

Pg 272, FIgure 4.12: ALU control input for CBZ should be 0011

Pg 273, Figure 4.13: Second row operation should be 0011

Pg 276 Figure 4.16: ALUSrc: the number of bits extended is NOT 16, but instead depends on the instruction type and varies between 9 and 26 bits.

Pg 301, 1. Instruction fetch.  Where it says "This incremented address is also saved in the IF/ID pipeline register in case..." it should say "The (unincremented) PC address is also stored in the IF/ID pipeline register in case...". 

Pg 301, 2. Instruction decoe and register file read.  Where it says "along witht the incremented PC address" it should say "along with the PC address"

Pg 304, Figure 4.37, Top, in far right MUX, the 0,1 inputs are switched

Pg 306, Figure 4.39, Top, in far right MUX, the 0,1 inputs are switched

Pg 322: The second line of each blue condition should be = (ie, instead of not equals).

Pg 325, Figure 4.57: SUB X2,X1,X3 should be LDUR X2,[X1,#20]

Pg 339, Figure 4.64: The upper arrow to the =0 unit shouldn't be there.

Pg 340: "Note that the address of the instruction following the ADD is saved".  This is incorrect: the address of the ADD (4C) is saved.

Pg 402: "because an n-bit field has 2n values" should be "2^n values"

Figure 4.63, EX/MEM and MEM/WB pipeline register labels are swapped.

Appendix A, pg A-9: decoder margin note: should say 2^n outputs

Appendix A, pg A-10: At the end of the first paragraph, the formula should be C=(A bS) + (B S).

Appendix A, pg A-11: The second equation for E should have a + instead of . between the second and third product terms (see page A-7).

Appendix A, pg A-12: In the truth table for the example, C should be an input, not an output.  And in the list of product terms following the table, the second one should be bA B bC.  And in the formula for D, the product terms should be combined with "+"s rather than multiplied.

Appendix A.3, pg A-19, Figure A.3.6: the number of bits in the inputs and outputs in the MUX on the left should be 64 (not 63).

Appendix A.3, pg A-20: the Check Yourself parity question: none of the columns are the correct answer.

Appendix A.5, pgs A-27 to A-33: The odd page header say "A.4 Constructing a Basic Arithmetic Logic Unit)"; it should say "A.5" instead of "A.4".

Appendix A, pg A-30: Figure A.5.7: caption says "64-bit ALU", figure is for 31-bit ALU.  The "31"s in the figure should be changed to "63"s.  Likewise, in discussing this figure on page A-29, the text refers to Result31 when it should say Result63.

Appendix A, pgs A-33 to A-35: 1-bit ALU is still MIPS version with set-less-than.  In particular,
		Figure A.5.10, top and bottom, the "Less" input should change its name to "Pass", and it should connect to 'b'.  Likewise, the "Set" output should dissappear.  
		Figure A.5.11 should NOT have Set bit from ALU31 going back to ALU0, and the "0" input to the other 31 ALUs should be removed.  And the bottom ALU should be ALU63.  Same in A.5.12, although the bottom ALU is correctly labeled ALU63.  
Appendix A, pg A-35:	Figure/Table A.5.13, should not have "set on less than" and should have "pass", with the ALU control signal for Pass being 0011.  

Appendix A, pg A-60: Figure A.9.3: the lines from the decoder outputs should extend all the way to the dots connecting to the enable lines of the right hand column of latches.  Also, the right Din[1] should be Din[0].

Appendix A, pg A-66: "if there are n bits of storage, there are 2n states" should say 2^n states.

Appendix C.2: The control unit designed here is for MIPS, not ARM.

Page A-86: Answers to Check Yourself: "A.5, page A-38:2" should say "A.5, page A-37: 1"