CS 452/652 Fall 2019 - Lecture 12

• interrupt raised by device
• interrupt routed by controller
• interrupt taken and processed by CPU

• Section 6.1.2 lists 64 numbered interrupt sources, among them:
• 3x timer underflow, several UART interrupts

• vectored interrupt processing
  • VIC determines interrupt service routine (ISR)
  • VIC determines priority
  • faster, but VIC setup/programming more complex
• central interrupt processing
  • single entry routine at 0x18/0x38, similar to SWI setup
  • software queries VIC status register to determine interrupt sources
  • software decides priority and invokes actual interrupt handler
  • recommendation: perform query and handling from kernel C/C++ code;
    keep context-switch assembly as simple as possible!
  • sufficient for CS 452 kernel; VIC setup simpler

• all IRQs disabled
• all FIQs disabled
• (all) vectored interrupts disabled

Interrupt Handling

Basics

• irq handler starts in IRQ mode, must eventually switch to SVC mode
• IRQ stack designated by IRQ mode's banked sp register → valid memory address?
• one or multiple kernel entry routines for SWI vs. IRQ possible

IRQ Context Switch

• return-to-task: task → IRQ → task
  • simple: use IRQ stack for task's execution context
  • example: record clock tick for later processing
  • example: record event on one core for later processing on another core
  • but: not used in CS 452 kernel
• preemption: task → IRQ → kernel → (other) task
  • dedicated IRQ/kernel stack per user task?
    • hardware-supported on Intel/AMD x86-64 architecture
    • could be emulated in software on ARM 920T?
    • mode switch user/kernel: callee-owned registers on thread's kernel stack
    • thread switch in kernel: caller-owned registers on thread's kernel stack
  • single kernel stack
    • default mode for ARM 920T - IRQ handler executes on single IRQ stack
    • all state is critical ⇒ (at least temporarily) push some info on IRQ stack
    • obtain and save user execution state
    • transition to SVC stack for kernel execution
• here: always preempt, i.e., append current task to ready-queue and re-schedule!

Enter/Exit Kernel

• storage/layout of user state?
  • same for both SWI and IRQ entry
  • different and keep track of entry type
• enter/leave routine?
  • same: can dynamically detect IRQ handling via cpsr
  • different: can use assembler macros to avoid source code duplication

Interrupt Confirmation

• cause for interrupt (at device):
  • event, such as timer underflow → edge trigger
  • status, such as buffer empty → level trigger
• VIC → CPU: level signal
  • after completion of interrupt handler, interrupt would be triggered again!
  • event trigger → confirm at device
    • for example, confirm timer interrupt by writing to BASE + 0x0C.
  • level trigger → force status change or disable interrupt
    • we'll revisit this later for UART interrupts

Timer Interrupts

• device automatically generates interrupt, if timer is enabled
• timer underflow: interrupt when timer reaches 0 (timer continues and/or is reloaded)
• VIC must enable/disable/configure interrupt delivery
• CPU must accept interrupts (user mode)
• generic interrupt handler

    query VIC status register for interrupt source
    choose and process interrupt
    make current task ready
    schedule next task
  

• timer interrupt: confirm interrupt before/during/after processing