CS452 F23 Lecture Notes
Lecture 04 - 19 Sep 2023
1. One View: Generic Kernel Loop
void kmain() {
initialize();; // includes creating first user task
for(;;) {
cur_task = schedule();
request = activate(cur_task);
handle(request)
}
}
2. Another View: Kernel as Event Handler
- kernel is
- boot code
- similar to initialize() above
- creates and activates first task
- exception handler
- similar to handle(request) + schedule() + activate()
- boot code
3. System Call
- see ARM Programmers Guide, Ch 10
- synchronous exception - this is how a task asks the kernel for something
- in ARM, system call occurs when task executes
svc Ninstruction- there are also
hvcandsmcto request service from hypervisor or secure monitor (can’t be issued from EL0) - N is a 16 bit code (encoded in the instruction) used to indicate which kind of system call
- there are also
svc Ncauses the following- record exception code (0x15) and N in ESREL1 (exception syndrome register)
- only used for synchronous exceptions
- identifies exception type (e.g., svc) plus type-specific data
- for svc, register will hold 16 bit immediate value (N) encoded with
svn
- for svc, register will hold 16 bit immediate value (N) encoded with
- record task’s next PC in ELREL1 (exception link register)
- records task’s pstate in SPSREL1 (saved processor state register)
- switches processor to priviledged execution (EL1)
- processor has EL0, EL1, EL2, EL3 - we’re only using 0 and 1
- switches to use the EL1 stack pointer
- EL0 (task) stack pointer can also be accessed from the kernel
- sets PC to address determined by VBAREL1 and type of exception (sync, IRQ, FIQ, SError)
- VBAREL1 points to an exception vector for exceptions taken to EL1
- 4 groups of entries (from where)
- Current EL SP0/x, Lower EL 64/32
- we care about Lower EL 64
- Current EL SP0/x, Lower EL 64/32
- each group has 4 vectors (sync, IRQ, FIQ, SError)
- each entry has each with 128 bytes - first 32 instructions of an exception handler
- 4 groups of entries (from where)
- each entry holds (part of) an exception handler
- VBAREL1 points to an exception vector for exceptions taken to EL1
- record exception code (0x15) and N in ESREL1 (exception syndrome register)
- What does context switch need to do?
- save all the general purpose registers
- save the PC?
- no, save the elrel1, which records the next PC for the user program
- save the processor state?
- no, save the spsrel1, which records the user prog’s processor state
- save the SP
- need to save spel0 - not spel1
- why bother saving it - we’re already on a different stack
- because we might not return to the same user-level task
4. Assignment Advice
- keep it simple: avoid premature optimization
- start small, add functionality in small steps
- test and commit at each step
- Example:
- first: kernel initialization
- second: create initial user process and switch to it
- third: implement Yield() system call
- fourth: impelment Exit()
- and so on….