CS 452/652 Winter 2020 - Lecture 3

Polling Patterns

• generic polling loop

  for (;;) {
    if( c1 ) a1();
    if( c2 ) a2();
    ...
  }
  

  ⇒worst-case latency: sum of all actions

• higher-frequency input/condition 'c1':

  for (;;) {
    if( c1 ) a1();
    if( c2 ) a2();
    if( c1 ) a1();
    if( c3 ) a3();
    ...
  }
  

  ⇒worst-case latency: maximum of all actions

• latency still too high? break up action into parts

  for (;;) {
    if( c1 ) a1();
    if( c2 ) { a2.1(); a2half = true; }
    if( c1 ) a1();
    if( a2half ) { a2.2(); a2half = false; }
    ...
  }
  

Memory Layout

• TS-7200 RAM

  0x2000000	high end of 32 MB RAM
  0x0218000	historic Linux load/start address
  0x0100000	suggested load address
  0x0044F88	lowest possible load address
  0x0000000	low end of RAM

• at runtime: code, data, no heap, stack
• ELF file format - sections: text, data, bss
  • text and data are placed by RedBoot 'load' command
  • entry point is learned by RedBoot for 'go' command
  • bss section must be zeroed by program itself
  • RedBoot 'go' does not re-initialize the data section

C standard library

• a lot of C functionality comes from the C standard libray
• C standard library interfaces with operating system
• here: newlib, but no operating system kernel
  • limited functionality - no heap!
• using newlib routines that always need dynamic memory → not possible
• using newlib routines that might need dynamic memory → might be possible
  • if certain that heap-needing functionality not triggered
  • linker might still want to resolve heap-related program break symbol → fake it!

Serial Communication

• actual transmission happens in parallel to processing
  • transmission delay has latency impact
  • CPU impact only with busy-waiting
  • latency and throughput are very different characteristics!
• transmission vs. receiver processing?
  • communication with track's UART vs. execution of track operation
• flow control in RS-232
  • extra signals to indicate ability to send/receive: RTS/CTS
    • 5-wire RS-232 vs. 3-wire RS-232
  • here only: Clear-To-Send (CTS)
  • receiver signals to sender: ready to receive next byte
• 'Receive Status Register/Error Clear' register: indicates any errors
  • if set, discard byte and reset status

Timing

• 32-bit timer sufficient as absolute timing reference
• proper wall-clock time not needed
• TS-7200 RTC clock → use later for random seeding
• on being late vs. being slow: consider fixed-rate operations (25x/sec)

  for (;;) {
    op1();
    wait(40ms);
  }
  

  → compounding error ⇒ slow! proper approach:

  t = 0;
  for (;;) {
    op1();
    t += 40ms;
    wait( t - now() );
  }
  

  → everything takes time, so late, but not slow!