CS 452/652 Winter 2022 - Lecture 10

January 28, 2022 prev next

Timing Measurements

ARM 920T CPU Caches

ARM 920T Cache Setup

  • setup information in co-processor register p15
  • accessed via MCR/MRC instructions
    MCR{<cond>} p15, 0, <Rd>, <CRn>, <CRm>{, <opcode2>}
    MRC{<cond>} p15, 0, <Rd>, <CRn>, <CRm>{, <opcode2>}
  • <CRn> set to c1 for cache enable/disable
  • <CRn> set to c7 for cache operations
  • necessary operations