CS 452/652 Winter 2022 - Lecture 10

Timing Measurements

• duration of operation?
• first approximation:

  start := clock;
  operation;
  stop := clock;
  

  • overhead/duration of clock?
  • accuracy of clock?
  • variations in operation?
• inflate impact of operation:

  start := clock;
  loop N times:
    operation;
  endloop;
  stop := clock;
  

• compute average time and/or enhanced statistics
• potential overheads
  • loop execution (counter, branch) → if relevant, measure with nop
  • concurrent workflow requires start/stop coordination
  • warm-up period with non-regular performance
  • sometimes: dummy side effects needed to keep optimizer from eliding experiment code
• N must be large enough to mitigate impact of these overheads
• experiment duration?
  • fixed N - simple
  • fixed run-time - predictable, but more difficult to set up and run

ARM 920T CPU Caches

• various caches
  • L1 instruction cache; L1 data cache
  • branch target cache (branch predictors)
  • TLB (page translation cache)
  • write buffer: mediate fast CPU ↔ slow RAM; coalesce writes
• ARM 920T caching modes (marked in page descriptor)
  0. non-cached, non-buffered → synchronous
  1. non-cached, buffered → ordered
  2. write-through, buffered → cache always clean
  3. write-back, buffered → most efficient
• default configuration
  • L1 caches separate (not unified)
  • no L2 cache?
  • no lockdown
  • regular memory in write-back mode
  • device memory in non-cached mode
  • RedBoot disables L1 caches during 'go' command

ARM 920T Cache Setup

MCR{<cond>} p15, 0, <Rd>, <CRn>, <CRm>{, <opcode2>}
MRC{<cond>} p15, 0, <Rd>, <CRn>, <CRm>{, <opcode2>}