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1 /*
2 * Copyright (c) 2000, 2001, 2002, 2003, 2004, 2005, 2008, 2009
3 * The President and Fellows of Harvard College.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the University nor the names of its contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #ifndef _MIPS_SPECIALREG_H_
31 #define _MIPS_SPECIALREG_H_
32
33
34 /*
35 * Coprocessor 0 (system processor) register numbers
36 */
37 #define c0_index $0 /* TLB entry index register */
38 #define c0_random $1 /* TLB random slot register */
39 #define c0_entrylo $2 /* TLB entry contents (low-order half) */
40 /* c0_entrylo0 $2 */ /* MIPS-II and up only */
41 /* c0_entrylo1 $3 */ /* MIPS-II and up only */
42 #define c0_context $4 /* some precomputed pagetable stuff */
43 /* c0_pagemask $5 */ /* MIPS-II and up only */
44 /* c0_wired $6 */ /* MIPS-II and up only */
45 #define c0_vaddr $8 /* virtual addr of failing memory access */
46 #define c0_count $9 /* cycle counter (MIPS-II and up) */
47 #define c0_entryhi $10 /* TLB entry contents (high-order half) */
48 #define c0_compare $11 /* on-chip timer control (MIPS-II and up) */
49 #define c0_status $12 /* processor status register */
50 #define c0_cause $13 /* exception cause register */
51 #define c0_epc $14 /* exception PC register */
52 #define c0_prid $15 /* processor ID register */
53 /* c0_config $16 */ /* MIPS-II and up only */
54 /* c0_lladdr $17 */ /* MIPS-II and up only */
55 /* c0_watchlo $18 */ /* MIPS-II and up only */
56 /* c0_watchhi $19 */ /* MIPS-II and up only */
57
58 /*
59 * Mode bits in c0_status
60 */
61 #define CST_IEc 0x00000001 /* current: interrupt enable */
62 #define CST_KUc 0x00000002 /* current: user mode */
63 #define CST_IEp 0x00000004 /* previous: interrupt enable */
64 #define CST_KUp 0x00000008 /* previous: user mode */
65 #define CST_IEo 0x00000010 /* old: interrupt enable */
66 #define CST_KUo 0x00000020 /* old: user mode */
67 #define CST_MODEMASK 0x0000003f /* mask for the above */
68 #define CST_IRQMASK 0x0000ff00 /* mask for the individual irq enable bits */
69 #define CST_BEV 0x00400000 /* bootstrap exception vectors flag */
70
71 /*
72 * Fields of the c0_cause register
73 */
74 #define CCA_UTLB 0x00000001 /* true if UTLB exception (set by our asm) */
75 #define CCA_CODE 0x0000003c /* EX_foo in trapframe.h */
76 #define CCA_IRQS 0x0000ff00 /* Currently pending interrupts */
77 #define CCA_COPN 0x30000000 /* Coprocessor number for EX_CPU */
78 #define CCA_JD 0x80000000 /* True if exception happened in jump delay */
79
80 #define CCA_CODESHIFT 2 /* shift for CCA_CODE field */
81
82 /*
83 * Fields of the c0_index register
84 */
85 #define CIN_P 0x80000000 /* nonzero -> TLB probe found nothing */
86 #define CIN_INDEX 0x00003f00 /* 6-bit index into TLB */
87
88 #define CIN_INDEXSHIFT 8 /* shift for CIN_INDEX field */
89
90 /*
91 * Fields of the c0_context register
92 *
93 * The intent of c0_context is that you can manage virtually-mapped
94 * page tables in kseg2; then you load the base address of the current
95 * page table into c0_context. On a TLB miss the failing address is
96 * masked and shifted and appears in the VSHIFT field, and c0_context
97 * thereby contains the address of the page table entry you need to
98 * load into the TLB. This can be used to make TLB refill very fast.
99 *
100 * However, in OS/161 we use CTX_PTBASE to hold the current CPU
101 * number. This (or something like it) is fairly important to have and
102 * there's no other good place in the chip to put it. See discussions
103 * elsewhere.
104 */
105 #define CTX_VSHIFT 0x001ffffc /* shifted/masked copy of c0_vaddr */
106 #define CTX_PTBASE 0xffe00000 /* page table base address */
107
108 #define CTX_PTBASESHIFT 21 /* shift for CTX_PBASE field */
109
110 /*
111 * Hardwired exception handler addresses.
112 */
113 #define EXADDR_UTLB 0x80000000
114 #define EXADDR_GENERAL 0x80000080
115
116
117 #endif /* _MIPS_SPECIALREG_H_ */