root/kern/arch/mips/include/tlb.h

INCLUDED FROM

   1 /*
   2  * Copyright (c) 2000, 2001, 2002, 2003, 2004, 2005, 2008, 2009
   3  *      The President and Fellows of Harvard College.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. Neither the name of the University nor the names of its contributors
  14  *    may be used to endorse or promote products derived from this software
  15  *    without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE UNIVERSITY OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  */
  30 #ifndef _MIPS_TLB_H_
  31 #define _MIPS_TLB_H_
  33 /*
  34  * MIPS-specific TLB access functions.
  35  *
  36  *   tlb_random: write the TLB entry specified by ENTRYHI and ENTRYLO
  37  *        into a "random" TLB slot chosen by the processor.
  38  *
  39  *        IMPORTANT NOTE: never write more than one TLB entry with the
  40  *        same virtual page field.
  41  *
  42  *   tlb_write: same as tlb_random, but you choose the slot.
  43  *
  44  *   tlb_read: read a TLB entry out of the TLB into ENTRYHI and ENTRYLO.
  45  *        INDEX specifies which one to get.
  46  *
  47  *   tlb_probe: look for an entry matching the virtual page in ENTRYHI.
  48  *        Returns the index, or a negative number if no matching entry
  49  *        was found. ENTRYLO is not actually used, but must be set; 0
  50  *        should be passed.
  51  *
  52  *        IMPORTANT NOTE: An entry may be matching even if the valid bit 
  53  *        is not set. To completely invalidate the TLB, load it with
  54  *        translations for addresses in one of the unmapped address
  55  *        ranges - these will never be matched.
  56  */
  58 void tlb_random(uint32_t entryhi, uint32_t entrylo);
  59 void tlb_write(uint32_t entryhi, uint32_t entrylo, uint32_t index);
  60 void tlb_read(uint32_t *entryhi, uint32_t *entrylo, uint32_t index);
  61 int tlb_probe(uint32_t entryhi, uint32_t entrylo);
  63 /*
  64  * TLB entry fields.
  65  *
  66  * Note that the MIPS has support for a 6-bit address space ID. In the
  67  * interests of simplicity, we don't use it. The fields related to it
  68  * (TLBLO_GLOBAL and TLBHI_PID) can be left always zero, as can the
  69  * bits that aren't assigned a meaning.
  70  *
  71  * The TLBLO_DIRTY bit is actually a write privilege bit - it is not
  72  * ever set by the processor. If you set it, writes are permitted. If
  73  * you don't set it, you'll get a "TLB Modify" exception when a write
  74  * is attempted.
  75  *
  76  * There is probably no reason in the course of CS161 to use TLBLO_NOCACHE.
  77  */
  79 /* Fields in the high-order word */
  80 #define TLBHI_VPAGE   0xfffff000
  81 /*      TLBHI_PID     0x00000fc0 */
  83 /* Fields in the low-order word */
  84 #define TLBLO_PPAGE   0xfffff000
  85 #define TLBLO_NOCACHE 0x00000800
  86 #define TLBLO_DIRTY   0x00000400
  87 #define TLBLO_VALID   0x00000200
  88 /*      TLBLO_GLOBAL  0x00000100 */
  90 /*
  91  * Values for completely invalid TLB entries. The TLB entry index should
  92  * be passed to TLBHI_INVALID; this prevents loading the same invalid
  93  * entry into multiple TLB slots.
  94  */
  95 #define TLBHI_INVALID(entryno) ((0x80000+(entryno))<<12)
  96 #define TLBLO_INVALID()        (0)
  98 /*
  99  * Number of TLB entries in the processor.
 100  */
 102 #define NUM_TLB  64
 105 #endif /* _MIPS_TLB_H_ */