- trivial design (in sample code) not sufficient:
// flags, data hold pointers to memory-mapped device register
while (*flags & TXFF_MASK);
*data = c;
- CPU unable to attend to other input signals
- e.g., 80-byte string to terminal: ~7ms
- software buffer: control size per direction
- hardware buffer (UART): fixed size for both directions!
- generic polling loop
for (;;) {
if( c1 ) a1;
if( c2 ) a2;
...
}
⇒worst-case latency: sum of all actions
- higher-frequency input/condition 'c1':
for (;;) {
if( c1 ) a1;
if( c2 ) a2;
if( c1 ) a1;
if( c3 ) a3;
...
}
⇒worst-case latency: maximum of all actions
- latency still too high? break up action into parts
for (;;) {
if( c1 ) a1;
if( c2 ) { a2.1; a2half = true; }
if( c1 ) a1;
if( a2half ) { a2.2; a2half = false; }
...
}
- not necessary for trains project - why?