This is a planned schedule; the schedule will be updated through the term to reflect the lectures actually given.
| Date | Topic | Readings (*'ed are optional) |
|---|---|---|
| Sep 4 | Introduction/overview, admin, ARM. | ARM Overview, ARM Reference Sheet |
| Sep 9 | 1st, 2nd, and 3rd simulator examples; performance | Chapter 2*, A2 (Truth tables), A3 (Circuits) |
| Sep 11 | Logic design, truth tables, minterms, don't cares; Boolean algebra, gates, Transistors through CMOS Not. | |
| Sep 16 | Finished transistors. Deriving Truth table, XOR; decoders, muxes. | A9,A64-A66 (Error Correction)*, Section 4.2 (Clocked Circuits), |
| Sep 18 | Clocks and sequential circuits; SR-latch. D-latch; D-flipflop; Register file. Started tri-state logic. | A7,A8 (Latches), A8 (Flip-flops) |
| Sep 23 | Tri-state; RAM. FSM; Simple traffic light example; | Section 5.2 (RAM), Appendix 9 (RAM) |
| Sep 24 | A1 due | |
| Sep 25 | Extended traffic light example, extended to pedestrians. | Appendix 10 (FSM) |
| Sep 30 | Breadboards, chips, building circuits. Hexidecimal, ASCII. Data representation, ripple carry adder, Bitwise Operations; |
Section 2.4 (Binary Numbers)
Section 3.2 (Binary Arithemtic) Section 2.6 (Shifting and Bitwise Operations) A5 (1-bit and 64-bit ALUs) Section 3.3 (Multiplication) |
| Oct 2 | Shifting, ALU; Multiplication. Floating point representation. | Section 3.5 (Floating Point), (Floating Point Historical Perspective)* |
| Oct 7 | Floating point addition, multiplication, accuracy. Single cycle computer: introduction. | Sections 4.1-4.4 (Single Cycle Datapath--READ THIS) |
| Oct 8 | A2 due | |
| Oct 9 | Started Single Cycle Computer Datapath. Review for midterm. | |
| Oct 11-19 | Reading week | |
| Oct 21 | Single Cycle Computer Examples. Lecture ended half an hour early. | |
| Oct 23 | SSC ALUcontrol, main control. SSC speed, | |
| Oct 28 | Modify single cycle datapath. Went over midterm. Introduction to pipelined computer. | Section 4.5 (Introduction to Pipelined Computer) |
| Oct 30 | Pipeline computer datapath, control. Pipelined computer-Hazards. Data hazards. NOPs. Forwarding. | Section 4.6 (Pipelined Datapath, Control--READ THIS)
Section 4.7 (Hazard--READ THIS) Section 4.8 (Control Hazards--READ THIS) |
| Nov 3 | A3 due | |
| Nov 4 | Pipelined stalls. Control hazards. Assume branch taken, 1-bit branch prediction. 2-bit branch prediction. | Section 4.9 (Exceptions), |
| Nov 5 | Midterm | |
| Nov 6 | Timing. Started Code rearrangment. Code Rearrangement. Exceptions. | |
| Nov 11 | Direct map cache. |
Section 5.1 (Memory Hierarchy) Section 5.3, Section 5.4 (Cache--READ THESE) Section 5.2 (Memory Technologies), |
| Nov 12 | A4 due | |
| Nov 13 | Block size cache. Array vs linked list code. Set associative caches through 2-way example. | |
| Nov 18 | Finished set associative caches. Splitting memory address into TAG,Index,Block, and Byte bits. LRU. | Section 5.7 (Virtual Memory--READ THIS) |
| Nov 20 | AMAT. Virtual Memory, | |
| Nov 24 | A5 due | |
| Nov 25 | Virtual Memory, TLB | Section 1.4 (Some on IO), Section 5.2 (later parts on IO) |
| Nov 27 | Multiprocessing.Microprogramming. Vax. SPARC. ARM, x86. | Section 6 (very long! only lightly read (skim) most parts) |
| Dec 1 | A6 due | |
| Dec 2 | HDD vs SSD. Review for final exam. | |
| TBA | FINAL EXAM |